The flexibility of programmable logic devices such as field programmable gate arrays (FPGAs) makes these devices attractive options for memory controller applications. However, should a memory controller need to interface with a multi-data rate synchronous dynamic random access memory such as DDR SDRAM, the use of FPGAs as memory controllers becomes challenging—the required I/O speeds and associated clocking becomes difficult to implement, particularly in view of the non-deterministic routing delays inherent in such devices and their often limited input/output (I/O) speeds. These challenges may be better understood with respect to the nature of a multi-data rate interface such as a DDR SDRAM interface.
Synchronous DRAM (SDRAM) differs from conventional DRAM in that both the memory clock and the system clock are synchronized to increase operating speeds. DDR SDRAM is even faster than SDRAM because data transfers occur on both edges of the memory clock, making DDR SDRAM a popular memory option. To accomplish their high-speed data transfers, DDR SDRAM interfaces rely on the use of a data strobe signal called DQS. An internal system clock from the FPGA is provided to the DDR SDRAM so that the DDR SDRAM may generate DQS and a data signal DQ that are edge aligned. Although DQS has the same frequency as the internal clock, their phase relationship is unpredictable. Regardless of this phase relationship, to correctly read the data at a corresponding DDR SDRAM interface input register, DQS must be phase-shifted by 90 degrees (delayed) with respect to DQ. A DDR SDRAM interface thus requires DQS-to-DQ phase alignment circuitry to accomplish this phase shift. Conventional FPGA DDR SDRAM interfaces use a fixed phase delay circuit to delay DQS (open loop operation). However, temperature changes, voltage changes, and semiconductor process variations will affect the generated delay such that the phase shift varies from the desired 90 degrees. Accordingly, there is a need in the art for a DDR SDRAM interface that adaptively controls the phase shift for the DQS signal.
In addition, data read by an FPGA from a DDR SDRAM must be multiplexed from its double data rate clock domain to a single data rate clock domain within the FPGA. As discussed previously, the single data rate clock domain is responsive to an internal FPGA system clock that has an unknown phase relationship to the DQS and DQ signals. Thus there is the problem of choosing the proper internal system clock edge to transfer data from the DQS domain to the internal clock domain. Conventional FPGA DDR SDRAM interfaces leave this selection problem to the user. Accordingly, there is a need in the art for DDR SDRAM interfaces that automatically select the proper internal clock edge for a DQS-to-system clock domain transfer.